The single electron transistor (SET) has become an essential element in electronics. The devices are operated by utilizing the Coulomb Blockade effect. However, the operation of SET device operation has been limited to below 4 K. The reason is that the smallest capacitance of the SET has been about 100 aF. This means that a charging energy e.sup.2 /(2 C) is much larger than the thermal energy, which could be met at very low temperature. In IEDM Tech. Dig. in the page 938 on 1994, Y. Takajashi et al. reported a Si-SET whose capacitance is only about 2 aF. The Si-SET is reported in this paper shows conductance oscillation even at room temperature is reported in this paper. Thus, using semiconductor technique, a SET can be fabricated in a substrate and it is operated at room temperature. In this paper, a process which is separation by implanted oxygen (SIMOX) is used to form a superficial Si layer. The SET device is fabricated in the superficial Si layer. Then, by using semiconductor technique, the author fabricated an one-dimensional Si wire in the superficial Si layer. The Si wire width can be in the order of nanometer.
Recently, the room temperature operation of a single-electron memory was realized by a device using nanometer-sized, polycrystalline fine-grain Si for a floating gate and channel. In IEDM Tech. Dig., in page 952 on 1996, A. Nakajima et al reported a Si single-electron memory with self-aligned floating gate. The authors reported a new Si single-electron memory device comprised of a narrow channel field effect transistor (FET) having an ultra-small self-aligned floating dot gate, which is capable to exhibit clear, single-electron memory effects at room temperature. In this paper, the Si single-electron FET memory has a width of about 30 nanometers and is operated at room temperature.
Many efforts are made to fabricate silicon-based SET devices. The smallest dimension required for SET operation depends on non-artificial process such as grain control and inhomogeneous oxidation, which can be hardly determined in the design stage. In page 955 of IEDM Tech. Dig. on 1996, L. Guo et al reported that a Si single-electron MOS memory (SEMM) is fabricated and the electrical characteristic of the device are detected. The device has a nanoscale floating-gate and a narrow gate. The capacitance for the 7 nm.times.7 nm floating gate and a 40 nm control oxide is 4.times.10.sup.-20 F, giving single electron charging voltage of 4 V. The SEMM device was fabricated by using silicon on insulator (SOI) technique. The channel of the device was fabricated using e-beam lithography and reactive ion etching. The channel had a width varying from 25 nm to 120 nm.
In page 4161 of vol. 36, Jpn. J. Appl. Phys., on 1997, N. Yoshikawa et al reported a single-electron-tunneling effect in nanoscale granular microbridge. The granular microbridge was fabricated on an oxide step. A thin film was deposited on the oxide step. An ion etching was performed at an angle of 45 degrees and a microbridge was formed beside the oxide step.
In the last two papers, the methods of fabricating the single electron channel are nonartifical and difficult to control. In another words, designers are hard to design a good structure and to control the dimension of the channel. Thus, a simple and stable process method to fabricate the single electron transistor is essentially necessary.